411 lines
6.9 KiB
Go
411 lines
6.9 KiB
Go
// Inferno utils/5c/5.out.h
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// https://bitbucket.org/inferno-os/inferno-os/src/master/utils/5c/5.out.h
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//
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// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
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// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
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// Portions Copyright © 1997-1999 Vita Nuova Limited
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// Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com)
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// Portions Copyright © 2004,2006 Bruce Ellis
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// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
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// Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others
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// Portions Copyright © 2009 The Go Authors. All rights reserved.
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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package arm
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import "github.com/twitchyliquid64/golang-asm/obj"
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//go:generate go run ../stringer.go -i $GOFILE -o anames.go -p arm
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const (
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NSNAME = 8
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NSYM = 50
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NREG = 16
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)
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/* -1 disables use of REGARG */
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const (
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REGARG = -1
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)
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const (
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REG_R0 = obj.RBaseARM + iota // must be 16-aligned
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REG_R1
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REG_R2
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REG_R3
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REG_R4
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REG_R5
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REG_R6
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REG_R7
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REG_R8
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REG_R9
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REG_R10
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REG_R11
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REG_R12
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REG_R13
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REG_R14
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REG_R15
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REG_F0 // must be 16-aligned
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REG_F1
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REG_F2
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REG_F3
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REG_F4
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REG_F5
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REG_F6
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REG_F7
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REG_F8
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REG_F9
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REG_F10
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REG_F11
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REG_F12
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REG_F13
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REG_F14
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REG_F15
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REG_FPSR // must be 2-aligned
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REG_FPCR
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REG_CPSR // must be 2-aligned
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REG_SPSR
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REGRET = REG_R0
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/* compiler allocates R1 up as temps */
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/* compiler allocates register variables R3 up */
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/* compiler allocates external registers R10 down */
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REGEXT = REG_R10
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/* these two registers are declared in runtime.h */
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REGG = REGEXT - 0
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REGM = REGEXT - 1
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REGCTXT = REG_R7
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REGTMP = REG_R11
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REGSP = REG_R13
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REGLINK = REG_R14
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REGPC = REG_R15
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NFREG = 16
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/* compiler allocates register variables F0 up */
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/* compiler allocates external registers F7 down */
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FREGRET = REG_F0
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FREGEXT = REG_F7
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FREGTMP = REG_F15
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)
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// http://infocenter.arm.com/help/topic/com.arm.doc.ihi0040b/IHI0040B_aadwarf.pdf
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var ARMDWARFRegisters = map[int16]int16{}
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func init() {
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// f assigns dwarfregisters[from:to] = (base):(step*(to-from)+base)
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f := func(from, to, base, step int16) {
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for r := int16(from); r <= to; r++ {
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ARMDWARFRegisters[r] = step*(r-from) + base
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}
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}
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f(REG_R0, REG_R15, 0, 1)
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f(REG_F0, REG_F15, 64, 2) // Use d0 through D15, aka S0, S2, ..., S30
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}
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// Special registers, after subtracting obj.RBaseARM, bit 9 indicates
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// a special register and the low bits select the register.
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const (
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REG_SPECIAL = obj.RBaseARM + 1<<9 + iota
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REG_MB_SY
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REG_MB_ST
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REG_MB_ISH
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REG_MB_ISHST
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REG_MB_NSH
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REG_MB_NSHST
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REG_MB_OSH
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REG_MB_OSHST
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MAXREG
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)
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const (
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C_NONE = iota
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C_REG
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C_REGREG
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C_REGREG2
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C_REGLIST
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C_SHIFT /* register shift R>>x */
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C_SHIFTADDR /* memory address with shifted offset R>>x(R) */
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C_FREG
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C_PSR
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C_FCR
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C_SPR /* REG_MB_SY */
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C_RCON /* 0xff rotated */
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C_NCON /* ~RCON */
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C_RCON2A /* OR of two disjoint C_RCON constants */
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C_RCON2S /* subtraction of two disjoint C_RCON constants */
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C_SCON /* 0xffff */
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C_LCON
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C_LCONADDR
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C_ZFCON
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C_SFCON
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C_LFCON
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C_RACON
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C_LACON
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C_SBRA
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C_LBRA
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C_HAUTO /* halfword insn offset (-0xff to 0xff) */
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C_FAUTO /* float insn offset (0 to 0x3fc, word aligned) */
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C_HFAUTO /* both H and F */
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C_SAUTO /* -0xfff to 0xfff */
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C_LAUTO
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C_HOREG
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C_FOREG
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C_HFOREG
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C_SOREG
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C_ROREG
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C_SROREG /* both nil and R */
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C_LOREG
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C_PC
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C_SP
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C_HREG
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C_ADDR /* reference to relocatable address */
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// TLS "var" in local exec mode: will become a constant offset from
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// thread local base that is ultimately chosen by the program linker.
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C_TLS_LE
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// TLS "var" in initial exec mode: will become a memory address (chosen
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// by the program linker) that the dynamic linker will fill with the
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// offset from the thread local base.
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C_TLS_IE
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C_TEXTSIZE
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C_GOK
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C_NCLASS /* must be the last */
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)
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const (
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AAND = obj.ABaseARM + obj.A_ARCHSPECIFIC + iota
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AEOR
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ASUB
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ARSB
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AADD
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AADC
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ASBC
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ARSC
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ATST
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ATEQ
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ACMP
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ACMN
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AORR
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ABIC
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AMVN
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/*
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* Do not reorder or fragment the conditional branch
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* opcodes, or the predication code will break
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*/
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ABEQ
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ABNE
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ABCS
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ABHS
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ABCC
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ABLO
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ABMI
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ABPL
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ABVS
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ABVC
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ABHI
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ABLS
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ABGE
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ABLT
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ABGT
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ABLE
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AMOVWD
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AMOVWF
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AMOVDW
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AMOVFW
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AMOVFD
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AMOVDF
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AMOVF
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AMOVD
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ACMPF
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ACMPD
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AADDF
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AADDD
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ASUBF
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ASUBD
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AMULF
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AMULD
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ANMULF
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ANMULD
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AMULAF
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AMULAD
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ANMULAF
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ANMULAD
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AMULSF
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AMULSD
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ANMULSF
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ANMULSD
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AFMULAF
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AFMULAD
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AFNMULAF
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AFNMULAD
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AFMULSF
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AFMULSD
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AFNMULSF
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AFNMULSD
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ADIVF
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ADIVD
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ASQRTF
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ASQRTD
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AABSF
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AABSD
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ANEGF
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ANEGD
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ASRL
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ASRA
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ASLL
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AMULU
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ADIVU
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AMUL
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AMMUL
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ADIV
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AMOD
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AMODU
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ADIVHW
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ADIVUHW
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AMOVB
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AMOVBS
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AMOVBU
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AMOVH
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AMOVHS
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AMOVHU
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AMOVW
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AMOVM
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ASWPBU
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ASWPW
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ARFE
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ASWI
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AMULA
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AMULS
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AMMULA
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AMMULS
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AWORD
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AMULL
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AMULAL
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AMULLU
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AMULALU
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ABX
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ABXRET
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ADWORD
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ALDREX
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ASTREX
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ALDREXD
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ASTREXD
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ADMB
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APLD
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ACLZ
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AREV
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AREV16
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AREVSH
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ARBIT
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AXTAB
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AXTAH
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AXTABU
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AXTAHU
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ABFX
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ABFXU
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ABFC
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ABFI
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AMULWT
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AMULWB
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AMULBB
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AMULAWT
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AMULAWB
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AMULABB
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AMRC // MRC/MCR
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ALAST
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// aliases
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AB = obj.AJMP
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ABL = obj.ACALL
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)
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/* scond byte */
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const (
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C_SCOND = (1 << 4) - 1
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C_SBIT = 1 << 4
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C_PBIT = 1 << 5
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C_WBIT = 1 << 6
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C_FBIT = 1 << 7 /* psr flags-only */
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C_UBIT = 1 << 7 /* up bit, unsigned bit */
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// These constants are the ARM condition codes encodings,
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// XORed with 14 so that C_SCOND_NONE has value 0,
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// so that a zeroed Prog.scond means "always execute".
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C_SCOND_XOR = 14
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C_SCOND_EQ = 0 ^ C_SCOND_XOR
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C_SCOND_NE = 1 ^ C_SCOND_XOR
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C_SCOND_HS = 2 ^ C_SCOND_XOR
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C_SCOND_LO = 3 ^ C_SCOND_XOR
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C_SCOND_MI = 4 ^ C_SCOND_XOR
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C_SCOND_PL = 5 ^ C_SCOND_XOR
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C_SCOND_VS = 6 ^ C_SCOND_XOR
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C_SCOND_VC = 7 ^ C_SCOND_XOR
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C_SCOND_HI = 8 ^ C_SCOND_XOR
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C_SCOND_LS = 9 ^ C_SCOND_XOR
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C_SCOND_GE = 10 ^ C_SCOND_XOR
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C_SCOND_LT = 11 ^ C_SCOND_XOR
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C_SCOND_GT = 12 ^ C_SCOND_XOR
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C_SCOND_LE = 13 ^ C_SCOND_XOR
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C_SCOND_NONE = 14 ^ C_SCOND_XOR
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C_SCOND_NV = 15 ^ C_SCOND_XOR
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/* D_SHIFT type */
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SHIFT_LL = 0 << 5
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SHIFT_LR = 1 << 5
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SHIFT_AR = 2 << 5
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SHIFT_RR = 3 << 5
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)
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