1458 lines
29 KiB
Go
1458 lines
29 KiB
Go
// cmd/9l/noop.c, cmd/9l/pass.c, cmd/9l/span.c from Vita Nuova.
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//
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// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
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// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
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// Portions Copyright © 1997-1999 Vita Nuova Limited
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// Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
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// Portions Copyright © 2004,2006 Bruce Ellis
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// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
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// Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
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// Portions Copyright © 2009 The Go Authors. All rights reserved.
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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package mips
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import (
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"github.com/twitchyliquid64/golang-asm/obj"
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"github.com/twitchyliquid64/golang-asm/objabi"
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"github.com/twitchyliquid64/golang-asm/sys"
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"encoding/binary"
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"fmt"
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"math"
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)
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func progedit(ctxt *obj.Link, p *obj.Prog, newprog obj.ProgAlloc) {
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c := ctxt0{ctxt: ctxt, newprog: newprog}
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p.From.Class = 0
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p.To.Class = 0
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// Rewrite JMP/JAL to symbol as TYPE_BRANCH.
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switch p.As {
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case AJMP,
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AJAL,
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ARET,
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obj.ADUFFZERO,
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obj.ADUFFCOPY:
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if p.To.Sym != nil {
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p.To.Type = obj.TYPE_BRANCH
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}
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}
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// Rewrite float constants to values stored in memory.
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switch p.As {
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case AMOVF:
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if p.From.Type == obj.TYPE_FCONST {
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f32 := float32(p.From.Val.(float64))
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if math.Float32bits(f32) == 0 {
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p.As = AMOVW
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p.From.Type = obj.TYPE_REG
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p.From.Reg = REGZERO
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break
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}
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p.From.Type = obj.TYPE_MEM
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p.From.Sym = ctxt.Float32Sym(f32)
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p.From.Name = obj.NAME_EXTERN
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p.From.Offset = 0
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}
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case AMOVD:
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if p.From.Type == obj.TYPE_FCONST {
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f64 := p.From.Val.(float64)
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if math.Float64bits(f64) == 0 && c.ctxt.Arch.Family == sys.MIPS64 {
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p.As = AMOVV
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p.From.Type = obj.TYPE_REG
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p.From.Reg = REGZERO
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break
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}
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p.From.Type = obj.TYPE_MEM
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p.From.Sym = ctxt.Float64Sym(f64)
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p.From.Name = obj.NAME_EXTERN
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p.From.Offset = 0
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}
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// Put >32-bit constants in memory and load them
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case AMOVV:
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if p.From.Type == obj.TYPE_CONST && p.From.Name == obj.NAME_NONE && p.From.Reg == 0 && int64(int32(p.From.Offset)) != p.From.Offset {
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p.From.Type = obj.TYPE_MEM
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p.From.Sym = ctxt.Int64Sym(p.From.Offset)
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p.From.Name = obj.NAME_EXTERN
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p.From.Offset = 0
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}
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}
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// Rewrite SUB constants into ADD.
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switch p.As {
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case ASUB:
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if p.From.Type == obj.TYPE_CONST {
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p.From.Offset = -p.From.Offset
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p.As = AADD
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}
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case ASUBU:
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if p.From.Type == obj.TYPE_CONST {
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p.From.Offset = -p.From.Offset
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p.As = AADDU
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}
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case ASUBV:
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if p.From.Type == obj.TYPE_CONST {
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p.From.Offset = -p.From.Offset
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p.As = AADDV
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}
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case ASUBVU:
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if p.From.Type == obj.TYPE_CONST {
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p.From.Offset = -p.From.Offset
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p.As = AADDVU
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}
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}
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}
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func preprocess(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
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// TODO(minux): add morestack short-cuts with small fixed frame-size.
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c := ctxt0{ctxt: ctxt, newprog: newprog, cursym: cursym}
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// a switch for enabling/disabling instruction scheduling
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nosched := true
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if c.cursym.Func.Text == nil || c.cursym.Func.Text.Link == nil {
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return
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}
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p := c.cursym.Func.Text
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textstksiz := p.To.Offset
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if textstksiz == -ctxt.FixedFrameSize() {
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// Historical way to mark NOFRAME.
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p.From.Sym.Set(obj.AttrNoFrame, true)
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textstksiz = 0
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}
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if textstksiz < 0 {
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c.ctxt.Diag("negative frame size %d - did you mean NOFRAME?", textstksiz)
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}
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if p.From.Sym.NoFrame() {
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if textstksiz != 0 {
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c.ctxt.Diag("NOFRAME functions must have a frame size of 0, not %d", textstksiz)
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}
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}
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c.cursym.Func.Args = p.To.Val.(int32)
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c.cursym.Func.Locals = int32(textstksiz)
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/*
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* find leaf subroutines
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* expand RET
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* expand BECOME pseudo
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*/
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for p := c.cursym.Func.Text; p != nil; p = p.Link {
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switch p.As {
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/* too hard, just leave alone */
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case obj.ATEXT:
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p.Mark |= LABEL | LEAF | SYNC
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if p.Link != nil {
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p.Link.Mark |= LABEL
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}
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/* too hard, just leave alone */
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case AMOVW,
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AMOVV:
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if p.To.Type == obj.TYPE_REG && p.To.Reg >= REG_SPECIAL {
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p.Mark |= LABEL | SYNC
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break
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}
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if p.From.Type == obj.TYPE_REG && p.From.Reg >= REG_SPECIAL {
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p.Mark |= LABEL | SYNC
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}
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/* too hard, just leave alone */
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case ASYSCALL,
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AWORD,
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ATLBWR,
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ATLBWI,
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ATLBP,
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ATLBR:
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p.Mark |= LABEL | SYNC
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case ANOR:
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if p.To.Type == obj.TYPE_REG {
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if p.To.Reg == REGZERO {
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p.Mark |= LABEL | SYNC
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}
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}
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case ABGEZAL,
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ABLTZAL,
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AJAL,
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obj.ADUFFZERO,
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obj.ADUFFCOPY:
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c.cursym.Func.Text.Mark &^= LEAF
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fallthrough
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case AJMP,
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ABEQ,
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ABGEZ,
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ABGTZ,
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ABLEZ,
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ABLTZ,
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ABNE,
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ABFPT, ABFPF:
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if p.As == ABFPT || p.As == ABFPF {
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// We don't treat ABFPT and ABFPF as branches here,
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// so that we will always fill nop (0x0) in their
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// delay slot during assembly.
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// This is to workaround a kernel FPU emulator bug
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// where it uses the user stack to simulate the
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// instruction in the delay slot if it's not 0x0,
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// and somehow that leads to SIGSEGV when the kernel
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// jump to the stack.
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p.Mark |= SYNC
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} else {
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p.Mark |= BRANCH
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}
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q1 := p.To.Target()
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if q1 != nil {
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for q1.As == obj.ANOP {
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q1 = q1.Link
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p.To.SetTarget(q1)
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}
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if q1.Mark&LEAF == 0 {
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q1.Mark |= LABEL
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}
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}
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//else {
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// p.Mark |= LABEL
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//}
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q1 = p.Link
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if q1 != nil {
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q1.Mark |= LABEL
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}
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case ARET:
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if p.Link != nil {
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p.Link.Mark |= LABEL
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}
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}
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}
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var mov, add obj.As
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if c.ctxt.Arch.Family == sys.MIPS64 {
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add = AADDV
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mov = AMOVV
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} else {
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add = AADDU
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mov = AMOVW
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}
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var q *obj.Prog
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var q1 *obj.Prog
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autosize := int32(0)
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var p1 *obj.Prog
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var p2 *obj.Prog
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for p := c.cursym.Func.Text; p != nil; p = p.Link {
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o := p.As
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switch o {
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case obj.ATEXT:
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autosize = int32(textstksiz)
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if p.Mark&LEAF != 0 && autosize == 0 {
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// A leaf function with no locals has no frame.
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p.From.Sym.Set(obj.AttrNoFrame, true)
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}
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if !p.From.Sym.NoFrame() {
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// If there is a stack frame at all, it includes
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// space to save the LR.
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autosize += int32(c.ctxt.FixedFrameSize())
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}
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if autosize&4 != 0 && c.ctxt.Arch.Family == sys.MIPS64 {
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autosize += 4
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}
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if autosize == 0 && c.cursym.Func.Text.Mark&LEAF == 0 {
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if c.cursym.Func.Text.From.Sym.NoSplit() {
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if ctxt.Debugvlog {
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ctxt.Logf("save suppressed in: %s\n", c.cursym.Name)
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}
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c.cursym.Func.Text.Mark |= LEAF
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}
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}
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p.To.Offset = int64(autosize) - ctxt.FixedFrameSize()
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if c.cursym.Func.Text.Mark&LEAF != 0 {
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c.cursym.Set(obj.AttrLeaf, true)
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if p.From.Sym.NoFrame() {
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break
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}
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}
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if !p.From.Sym.NoSplit() {
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p = c.stacksplit(p, autosize) // emit split check
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}
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q = p
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if autosize != 0 {
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// Make sure to save link register for non-empty frame, even if
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// it is a leaf function, so that traceback works.
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// Store link register before decrement SP, so if a signal comes
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// during the execution of the function prologue, the traceback
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// code will not see a half-updated stack frame.
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// This sequence is not async preemptible, as if we open a frame
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// at the current SP, it will clobber the saved LR.
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q = c.ctxt.StartUnsafePoint(q, c.newprog)
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q = obj.Appendp(q, newprog)
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q.As = mov
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q.Pos = p.Pos
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q.From.Type = obj.TYPE_REG
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q.From.Reg = REGLINK
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q.To.Type = obj.TYPE_MEM
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q.To.Offset = int64(-autosize)
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q.To.Reg = REGSP
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q = obj.Appendp(q, newprog)
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q.As = add
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q.Pos = p.Pos
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q.From.Type = obj.TYPE_CONST
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q.From.Offset = int64(-autosize)
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q.To.Type = obj.TYPE_REG
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q.To.Reg = REGSP
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q.Spadj = +autosize
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q = c.ctxt.EndUnsafePoint(q, c.newprog, -1)
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}
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if c.cursym.Func.Text.From.Sym.Wrapper() && c.cursym.Func.Text.Mark&LEAF == 0 {
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// if(g->panic != nil && g->panic->argp == FP) g->panic->argp = bottom-of-frame
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//
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// MOV g_panic(g), R1
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// BEQ R1, end
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// MOV panic_argp(R1), R2
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// ADD $(autosize+FIXED_FRAME), R29, R3
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// BNE R2, R3, end
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// ADD $FIXED_FRAME, R29, R2
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// MOV R2, panic_argp(R1)
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// end:
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// NOP
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//
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// The NOP is needed to give the jumps somewhere to land.
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// It is a liblink NOP, not an mips NOP: it encodes to 0 instruction bytes.
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//
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// We don't generate this for leafs because that means the wrapped
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// function was inlined into the wrapper.
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q = obj.Appendp(q, newprog)
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q.As = mov
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q.From.Type = obj.TYPE_MEM
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q.From.Reg = REGG
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q.From.Offset = 4 * int64(c.ctxt.Arch.PtrSize) // G.panic
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q.To.Type = obj.TYPE_REG
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q.To.Reg = REG_R1
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q = obj.Appendp(q, newprog)
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q.As = ABEQ
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q.From.Type = obj.TYPE_REG
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q.From.Reg = REG_R1
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q.To.Type = obj.TYPE_BRANCH
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q.Mark |= BRANCH
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p1 = q
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q = obj.Appendp(q, newprog)
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q.As = mov
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q.From.Type = obj.TYPE_MEM
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q.From.Reg = REG_R1
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q.From.Offset = 0 // Panic.argp
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q.To.Type = obj.TYPE_REG
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q.To.Reg = REG_R2
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q = obj.Appendp(q, newprog)
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q.As = add
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q.From.Type = obj.TYPE_CONST
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q.From.Offset = int64(autosize) + ctxt.FixedFrameSize()
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q.Reg = REGSP
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q.To.Type = obj.TYPE_REG
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q.To.Reg = REG_R3
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q = obj.Appendp(q, newprog)
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q.As = ABNE
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q.From.Type = obj.TYPE_REG
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q.From.Reg = REG_R2
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q.Reg = REG_R3
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q.To.Type = obj.TYPE_BRANCH
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q.Mark |= BRANCH
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p2 = q
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q = obj.Appendp(q, newprog)
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q.As = add
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q.From.Type = obj.TYPE_CONST
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q.From.Offset = ctxt.FixedFrameSize()
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q.Reg = REGSP
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q.To.Type = obj.TYPE_REG
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q.To.Reg = REG_R2
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q = obj.Appendp(q, newprog)
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q.As = mov
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q.From.Type = obj.TYPE_REG
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q.From.Reg = REG_R2
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q.To.Type = obj.TYPE_MEM
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q.To.Reg = REG_R1
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q.To.Offset = 0 // Panic.argp
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|
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q = obj.Appendp(q, newprog)
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|
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q.As = obj.ANOP
|
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p1.To.SetTarget(q)
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p2.To.SetTarget(q)
|
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}
|
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|
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case ARET:
|
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if p.From.Type == obj.TYPE_CONST {
|
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ctxt.Diag("using BECOME (%v) is not supported!", p)
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break
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}
|
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|
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retSym := p.To.Sym
|
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p.To.Name = obj.NAME_NONE // clear fields as we may modify p to other instruction
|
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p.To.Sym = nil
|
|
|
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if c.cursym.Func.Text.Mark&LEAF != 0 {
|
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if autosize == 0 {
|
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p.As = AJMP
|
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p.From = obj.Addr{}
|
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if retSym != nil { // retjmp
|
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p.To.Type = obj.TYPE_BRANCH
|
|
p.To.Name = obj.NAME_EXTERN
|
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p.To.Sym = retSym
|
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} else {
|
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p.To.Type = obj.TYPE_MEM
|
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p.To.Reg = REGLINK
|
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p.To.Offset = 0
|
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}
|
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p.Mark |= BRANCH
|
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break
|
|
}
|
|
|
|
p.As = add
|
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p.From.Type = obj.TYPE_CONST
|
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p.From.Offset = int64(autosize)
|
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p.To.Type = obj.TYPE_REG
|
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p.To.Reg = REGSP
|
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p.Spadj = -autosize
|
|
|
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q = c.newprog()
|
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q.As = AJMP
|
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q.Pos = p.Pos
|
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q.To.Type = obj.TYPE_MEM
|
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q.To.Offset = 0
|
|
q.To.Reg = REGLINK
|
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q.Mark |= BRANCH
|
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q.Spadj = +autosize
|
|
|
|
q.Link = p.Link
|
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p.Link = q
|
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break
|
|
}
|
|
|
|
p.As = mov
|
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p.From.Type = obj.TYPE_MEM
|
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p.From.Offset = 0
|
|
p.From.Reg = REGSP
|
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p.To.Type = obj.TYPE_REG
|
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p.To.Reg = REGLINK
|
|
|
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if autosize != 0 {
|
|
q = c.newprog()
|
|
q.As = add
|
|
q.Pos = p.Pos
|
|
q.From.Type = obj.TYPE_CONST
|
|
q.From.Offset = int64(autosize)
|
|
q.To.Type = obj.TYPE_REG
|
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q.To.Reg = REGSP
|
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q.Spadj = -autosize
|
|
|
|
q.Link = p.Link
|
|
p.Link = q
|
|
}
|
|
|
|
q1 = c.newprog()
|
|
q1.As = AJMP
|
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q1.Pos = p.Pos
|
|
if retSym != nil { // retjmp
|
|
q1.To.Type = obj.TYPE_BRANCH
|
|
q1.To.Name = obj.NAME_EXTERN
|
|
q1.To.Sym = retSym
|
|
} else {
|
|
q1.To.Type = obj.TYPE_MEM
|
|
q1.To.Offset = 0
|
|
q1.To.Reg = REGLINK
|
|
}
|
|
q1.Mark |= BRANCH
|
|
q1.Spadj = +autosize
|
|
|
|
q1.Link = q.Link
|
|
q.Link = q1
|
|
|
|
case AADD,
|
|
AADDU,
|
|
AADDV,
|
|
AADDVU:
|
|
if p.To.Type == obj.TYPE_REG && p.To.Reg == REGSP && p.From.Type == obj.TYPE_CONST {
|
|
p.Spadj = int32(-p.From.Offset)
|
|
}
|
|
|
|
case obj.AGETCALLERPC:
|
|
if cursym.Leaf() {
|
|
/* MOV LR, Rd */
|
|
p.As = mov
|
|
p.From.Type = obj.TYPE_REG
|
|
p.From.Reg = REGLINK
|
|
} else {
|
|
/* MOV (RSP), Rd */
|
|
p.As = mov
|
|
p.From.Type = obj.TYPE_MEM
|
|
p.From.Reg = REGSP
|
|
}
|
|
}
|
|
}
|
|
|
|
if c.ctxt.Arch.Family == sys.MIPS {
|
|
// rewrite MOVD into two MOVF in 32-bit mode to avoid unaligned memory access
|
|
for p = c.cursym.Func.Text; p != nil; p = p1 {
|
|
p1 = p.Link
|
|
|
|
if p.As != AMOVD {
|
|
continue
|
|
}
|
|
if p.From.Type != obj.TYPE_MEM && p.To.Type != obj.TYPE_MEM {
|
|
continue
|
|
}
|
|
|
|
p.As = AMOVF
|
|
q = c.newprog()
|
|
*q = *p
|
|
q.Link = p.Link
|
|
p.Link = q
|
|
p1 = q.Link
|
|
|
|
var addrOff int64
|
|
if c.ctxt.Arch.ByteOrder == binary.BigEndian {
|
|
addrOff = 4 // swap load/save order
|
|
}
|
|
if p.From.Type == obj.TYPE_MEM {
|
|
reg := REG_F0 + (p.To.Reg-REG_F0)&^1
|
|
p.To.Reg = reg
|
|
q.To.Reg = reg + 1
|
|
p.From.Offset += addrOff
|
|
q.From.Offset += 4 - addrOff
|
|
} else if p.To.Type == obj.TYPE_MEM {
|
|
reg := REG_F0 + (p.From.Reg-REG_F0)&^1
|
|
p.From.Reg = reg
|
|
q.From.Reg = reg + 1
|
|
p.To.Offset += addrOff
|
|
q.To.Offset += 4 - addrOff
|
|
}
|
|
}
|
|
}
|
|
|
|
if nosched {
|
|
// if we don't do instruction scheduling, simply add
|
|
// NOP after each branch instruction.
|
|
for p = c.cursym.Func.Text; p != nil; p = p.Link {
|
|
if p.Mark&BRANCH != 0 {
|
|
c.addnop(p)
|
|
}
|
|
}
|
|
return
|
|
}
|
|
|
|
// instruction scheduling
|
|
q = nil // p - 1
|
|
q1 = c.cursym.Func.Text // top of block
|
|
o := 0 // count of instructions
|
|
for p = c.cursym.Func.Text; p != nil; p = p1 {
|
|
p1 = p.Link
|
|
o++
|
|
if p.Mark&NOSCHED != 0 {
|
|
if q1 != p {
|
|
c.sched(q1, q)
|
|
}
|
|
for ; p != nil; p = p.Link {
|
|
if p.Mark&NOSCHED == 0 {
|
|
break
|
|
}
|
|
q = p
|
|
}
|
|
p1 = p
|
|
q1 = p
|
|
o = 0
|
|
continue
|
|
}
|
|
if p.Mark&(LABEL|SYNC) != 0 {
|
|
if q1 != p {
|
|
c.sched(q1, q)
|
|
}
|
|
q1 = p
|
|
o = 1
|
|
}
|
|
if p.Mark&(BRANCH|SYNC) != 0 {
|
|
c.sched(q1, p)
|
|
q1 = p1
|
|
o = 0
|
|
}
|
|
if o >= NSCHED {
|
|
c.sched(q1, p)
|
|
q1 = p1
|
|
o = 0
|
|
}
|
|
q = p
|
|
}
|
|
}
|
|
|
|
func (c *ctxt0) stacksplit(p *obj.Prog, framesize int32) *obj.Prog {
|
|
var mov, add, sub obj.As
|
|
|
|
if c.ctxt.Arch.Family == sys.MIPS64 {
|
|
add = AADDV
|
|
mov = AMOVV
|
|
sub = ASUBVU
|
|
} else {
|
|
add = AADDU
|
|
mov = AMOVW
|
|
sub = ASUBU
|
|
}
|
|
|
|
// MOV g_stackguard(g), R1
|
|
p = obj.Appendp(p, c.newprog)
|
|
|
|
p.As = mov
|
|
p.From.Type = obj.TYPE_MEM
|
|
p.From.Reg = REGG
|
|
p.From.Offset = 2 * int64(c.ctxt.Arch.PtrSize) // G.stackguard0
|
|
if c.cursym.CFunc() {
|
|
p.From.Offset = 3 * int64(c.ctxt.Arch.PtrSize) // G.stackguard1
|
|
}
|
|
p.To.Type = obj.TYPE_REG
|
|
p.To.Reg = REG_R1
|
|
|
|
// Mark the stack bound check and morestack call async nonpreemptible.
|
|
// If we get preempted here, when resumed the preemption request is
|
|
// cleared, but we'll still call morestack, which will double the stack
|
|
// unnecessarily. See issue #35470.
|
|
p = c.ctxt.StartUnsafePoint(p, c.newprog)
|
|
|
|
var q *obj.Prog
|
|
if framesize <= objabi.StackSmall {
|
|
// small stack: SP < stackguard
|
|
// AGTU SP, stackguard, R1
|
|
p = obj.Appendp(p, c.newprog)
|
|
|
|
p.As = ASGTU
|
|
p.From.Type = obj.TYPE_REG
|
|
p.From.Reg = REGSP
|
|
p.Reg = REG_R1
|
|
p.To.Type = obj.TYPE_REG
|
|
p.To.Reg = REG_R1
|
|
} else if framesize <= objabi.StackBig {
|
|
// large stack: SP-framesize < stackguard-StackSmall
|
|
// ADD $-(framesize-StackSmall), SP, R2
|
|
// SGTU R2, stackguard, R1
|
|
p = obj.Appendp(p, c.newprog)
|
|
|
|
p.As = add
|
|
p.From.Type = obj.TYPE_CONST
|
|
p.From.Offset = -(int64(framesize) - objabi.StackSmall)
|
|
p.Reg = REGSP
|
|
p.To.Type = obj.TYPE_REG
|
|
p.To.Reg = REG_R2
|
|
|
|
p = obj.Appendp(p, c.newprog)
|
|
p.As = ASGTU
|
|
p.From.Type = obj.TYPE_REG
|
|
p.From.Reg = REG_R2
|
|
p.Reg = REG_R1
|
|
p.To.Type = obj.TYPE_REG
|
|
p.To.Reg = REG_R1
|
|
} else {
|
|
// Such a large stack we need to protect against wraparound.
|
|
// If SP is close to zero:
|
|
// SP-stackguard+StackGuard <= framesize + (StackGuard-StackSmall)
|
|
// The +StackGuard on both sides is required to keep the left side positive:
|
|
// SP is allowed to be slightly below stackguard. See stack.h.
|
|
//
|
|
// Preemption sets stackguard to StackPreempt, a very large value.
|
|
// That breaks the math above, so we have to check for that explicitly.
|
|
// // stackguard is R1
|
|
// MOV $StackPreempt, R2
|
|
// BEQ R1, R2, label-of-call-to-morestack
|
|
// ADD $StackGuard, SP, R2
|
|
// SUB R1, R2
|
|
// MOV $(framesize+(StackGuard-StackSmall)), R1
|
|
// SGTU R2, R1, R1
|
|
p = obj.Appendp(p, c.newprog)
|
|
|
|
p.As = mov
|
|
p.From.Type = obj.TYPE_CONST
|
|
p.From.Offset = objabi.StackPreempt
|
|
p.To.Type = obj.TYPE_REG
|
|
p.To.Reg = REG_R2
|
|
|
|
p = obj.Appendp(p, c.newprog)
|
|
q = p
|
|
p.As = ABEQ
|
|
p.From.Type = obj.TYPE_REG
|
|
p.From.Reg = REG_R1
|
|
p.Reg = REG_R2
|
|
p.To.Type = obj.TYPE_BRANCH
|
|
p.Mark |= BRANCH
|
|
|
|
p = obj.Appendp(p, c.newprog)
|
|
p.As = add
|
|
p.From.Type = obj.TYPE_CONST
|
|
p.From.Offset = int64(objabi.StackGuard)
|
|
p.Reg = REGSP
|
|
p.To.Type = obj.TYPE_REG
|
|
p.To.Reg = REG_R2
|
|
|
|
p = obj.Appendp(p, c.newprog)
|
|
p.As = sub
|
|
p.From.Type = obj.TYPE_REG
|
|
p.From.Reg = REG_R1
|
|
p.To.Type = obj.TYPE_REG
|
|
p.To.Reg = REG_R2
|
|
|
|
p = obj.Appendp(p, c.newprog)
|
|
p.As = mov
|
|
p.From.Type = obj.TYPE_CONST
|
|
p.From.Offset = int64(framesize) + int64(objabi.StackGuard) - objabi.StackSmall
|
|
p.To.Type = obj.TYPE_REG
|
|
p.To.Reg = REG_R1
|
|
|
|
p = obj.Appendp(p, c.newprog)
|
|
p.As = ASGTU
|
|
p.From.Type = obj.TYPE_REG
|
|
p.From.Reg = REG_R2
|
|
p.Reg = REG_R1
|
|
p.To.Type = obj.TYPE_REG
|
|
p.To.Reg = REG_R1
|
|
}
|
|
|
|
// q1: BNE R1, done
|
|
p = obj.Appendp(p, c.newprog)
|
|
q1 := p
|
|
|
|
p.As = ABNE
|
|
p.From.Type = obj.TYPE_REG
|
|
p.From.Reg = REG_R1
|
|
p.To.Type = obj.TYPE_BRANCH
|
|
p.Mark |= BRANCH
|
|
|
|
// MOV LINK, R3
|
|
p = obj.Appendp(p, c.newprog)
|
|
|
|
p.As = mov
|
|
p.From.Type = obj.TYPE_REG
|
|
p.From.Reg = REGLINK
|
|
p.To.Type = obj.TYPE_REG
|
|
p.To.Reg = REG_R3
|
|
if q != nil {
|
|
q.To.SetTarget(p)
|
|
p.Mark |= LABEL
|
|
}
|
|
|
|
p = c.ctxt.EmitEntryStackMap(c.cursym, p, c.newprog)
|
|
|
|
// JAL runtime.morestack(SB)
|
|
p = obj.Appendp(p, c.newprog)
|
|
|
|
p.As = AJAL
|
|
p.To.Type = obj.TYPE_BRANCH
|
|
if c.cursym.CFunc() {
|
|
p.To.Sym = c.ctxt.Lookup("runtime.morestackc")
|
|
} else if !c.cursym.Func.Text.From.Sym.NeedCtxt() {
|
|
p.To.Sym = c.ctxt.Lookup("runtime.morestack_noctxt")
|
|
} else {
|
|
p.To.Sym = c.ctxt.Lookup("runtime.morestack")
|
|
}
|
|
p.Mark |= BRANCH
|
|
|
|
p = c.ctxt.EndUnsafePoint(p, c.newprog, -1)
|
|
|
|
// JMP start
|
|
p = obj.Appendp(p, c.newprog)
|
|
|
|
p.As = AJMP
|
|
p.To.Type = obj.TYPE_BRANCH
|
|
p.To.SetTarget(c.cursym.Func.Text.Link)
|
|
p.Mark |= BRANCH
|
|
|
|
// placeholder for q1's jump target
|
|
p = obj.Appendp(p, c.newprog)
|
|
|
|
p.As = obj.ANOP // zero-width place holder
|
|
q1.To.SetTarget(p)
|
|
|
|
return p
|
|
}
|
|
|
|
func (c *ctxt0) addnop(p *obj.Prog) {
|
|
q := c.newprog()
|
|
q.As = ANOOP
|
|
q.Pos = p.Pos
|
|
q.Link = p.Link
|
|
p.Link = q
|
|
}
|
|
|
|
const (
|
|
E_HILO = 1 << 0
|
|
E_FCR = 1 << 1
|
|
E_MCR = 1 << 2
|
|
E_MEM = 1 << 3
|
|
E_MEMSP = 1 << 4 /* uses offset and size */
|
|
E_MEMSB = 1 << 5 /* uses offset and size */
|
|
ANYMEM = E_MEM | E_MEMSP | E_MEMSB
|
|
//DELAY = LOAD|BRANCH|FCMP
|
|
DELAY = BRANCH /* only schedule branch */
|
|
)
|
|
|
|
type Dep struct {
|
|
ireg uint32
|
|
freg uint32
|
|
cc uint32
|
|
}
|
|
|
|
type Sch struct {
|
|
p obj.Prog
|
|
set Dep
|
|
used Dep
|
|
soffset int32
|
|
size uint8
|
|
nop uint8
|
|
comp bool
|
|
}
|
|
|
|
func (c *ctxt0) sched(p0, pe *obj.Prog) {
|
|
var sch [NSCHED]Sch
|
|
|
|
/*
|
|
* build side structure
|
|
*/
|
|
s := sch[:]
|
|
for p := p0; ; p = p.Link {
|
|
s[0].p = *p
|
|
c.markregused(&s[0])
|
|
if p == pe {
|
|
break
|
|
}
|
|
s = s[1:]
|
|
}
|
|
se := s
|
|
|
|
for i := cap(sch) - cap(se); i >= 0; i-- {
|
|
s = sch[i:]
|
|
if s[0].p.Mark&DELAY == 0 {
|
|
continue
|
|
}
|
|
if -cap(s) < -cap(se) {
|
|
if !conflict(&s[0], &s[1]) {
|
|
continue
|
|
}
|
|
}
|
|
|
|
var t []Sch
|
|
var j int
|
|
for j = cap(sch) - cap(s) - 1; j >= 0; j-- {
|
|
t = sch[j:]
|
|
if t[0].comp {
|
|
if s[0].p.Mark&BRANCH != 0 {
|
|
continue
|
|
}
|
|
}
|
|
if t[0].p.Mark&DELAY != 0 {
|
|
if -cap(s) >= -cap(se) || conflict(&t[0], &s[1]) {
|
|
continue
|
|
}
|
|
}
|
|
for u := t[1:]; -cap(u) <= -cap(s); u = u[1:] {
|
|
if c.depend(&u[0], &t[0]) {
|
|
continue
|
|
}
|
|
}
|
|
goto out2
|
|
}
|
|
|
|
if s[0].p.Mark&BRANCH != 0 {
|
|
s[0].nop = 1
|
|
}
|
|
continue
|
|
|
|
out2:
|
|
// t[0] is the instruction being moved to fill the delay
|
|
stmp := t[0]
|
|
copy(t[:i-j], t[1:i-j+1])
|
|
s[0] = stmp
|
|
|
|
if t[i-j-1].p.Mark&BRANCH != 0 {
|
|
// t[i-j] is being put into a branch delay slot
|
|
// combine its Spadj with the branch instruction
|
|
t[i-j-1].p.Spadj += t[i-j].p.Spadj
|
|
t[i-j].p.Spadj = 0
|
|
}
|
|
|
|
i--
|
|
}
|
|
|
|
/*
|
|
* put it all back
|
|
*/
|
|
var p *obj.Prog
|
|
var q *obj.Prog
|
|
for s, p = sch[:], p0; -cap(s) <= -cap(se); s, p = s[1:], q {
|
|
q = p.Link
|
|
if q != s[0].p.Link {
|
|
*p = s[0].p
|
|
p.Link = q
|
|
}
|
|
for s[0].nop != 0 {
|
|
s[0].nop--
|
|
c.addnop(p)
|
|
}
|
|
}
|
|
}
|
|
|
|
func (c *ctxt0) markregused(s *Sch) {
|
|
p := &s.p
|
|
s.comp = c.compound(p)
|
|
s.nop = 0
|
|
if s.comp {
|
|
s.set.ireg |= 1 << (REGTMP - REG_R0)
|
|
s.used.ireg |= 1 << (REGTMP - REG_R0)
|
|
}
|
|
|
|
ar := 0 /* dest is really reference */
|
|
ad := 0 /* source/dest is really address */
|
|
ld := 0 /* opcode is load instruction */
|
|
sz := 20 /* size of load/store for overlap computation */
|
|
|
|
/*
|
|
* flags based on opcode
|
|
*/
|
|
switch p.As {
|
|
case obj.ATEXT:
|
|
c.autosize = int32(p.To.Offset + 8)
|
|
ad = 1
|
|
|
|
case AJAL:
|
|
r := p.Reg
|
|
if r == 0 {
|
|
r = REGLINK
|
|
}
|
|
s.set.ireg |= 1 << uint(r-REG_R0)
|
|
ar = 1
|
|
ad = 1
|
|
|
|
case ABGEZAL,
|
|
ABLTZAL:
|
|
s.set.ireg |= 1 << (REGLINK - REG_R0)
|
|
fallthrough
|
|
case ABEQ,
|
|
ABGEZ,
|
|
ABGTZ,
|
|
ABLEZ,
|
|
ABLTZ,
|
|
ABNE:
|
|
ar = 1
|
|
ad = 1
|
|
|
|
case ABFPT,
|
|
ABFPF:
|
|
ad = 1
|
|
s.used.cc |= E_FCR
|
|
|
|
case ACMPEQD,
|
|
ACMPEQF,
|
|
ACMPGED,
|
|
ACMPGEF,
|
|
ACMPGTD,
|
|
ACMPGTF:
|
|
ar = 1
|
|
s.set.cc |= E_FCR
|
|
p.Mark |= FCMP
|
|
|
|
case AJMP:
|
|
ar = 1
|
|
ad = 1
|
|
|
|
case AMOVB,
|
|
AMOVBU:
|
|
sz = 1
|
|
ld = 1
|
|
|
|
case AMOVH,
|
|
AMOVHU:
|
|
sz = 2
|
|
ld = 1
|
|
|
|
case AMOVF,
|
|
AMOVW,
|
|
AMOVWL,
|
|
AMOVWR:
|
|
sz = 4
|
|
ld = 1
|
|
|
|
case AMOVD,
|
|
AMOVV,
|
|
AMOVVL,
|
|
AMOVVR:
|
|
sz = 8
|
|
ld = 1
|
|
|
|
case ADIV,
|
|
ADIVU,
|
|
AMUL,
|
|
AMULU,
|
|
AREM,
|
|
AREMU,
|
|
ADIVV,
|
|
ADIVVU,
|
|
AMULV,
|
|
AMULVU,
|
|
AREMV,
|
|
AREMVU:
|
|
s.set.cc = E_HILO
|
|
fallthrough
|
|
case AADD,
|
|
AADDU,
|
|
AADDV,
|
|
AADDVU,
|
|
AAND,
|
|
ANOR,
|
|
AOR,
|
|
ASGT,
|
|
ASGTU,
|
|
ASLL,
|
|
ASRA,
|
|
ASRL,
|
|
ASLLV,
|
|
ASRAV,
|
|
ASRLV,
|
|
ASUB,
|
|
ASUBU,
|
|
ASUBV,
|
|
ASUBVU,
|
|
AXOR,
|
|
|
|
AADDD,
|
|
AADDF,
|
|
AADDW,
|
|
ASUBD,
|
|
ASUBF,
|
|
ASUBW,
|
|
AMULF,
|
|
AMULD,
|
|
AMULW,
|
|
ADIVF,
|
|
ADIVD,
|
|
ADIVW:
|
|
if p.Reg == 0 {
|
|
if p.To.Type == obj.TYPE_REG {
|
|
p.Reg = p.To.Reg
|
|
}
|
|
//if(p->reg == NREG)
|
|
// print("botch %P\n", p);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* flags based on 'to' field
|
|
*/
|
|
cls := int(p.To.Class)
|
|
if cls == 0 {
|
|
cls = c.aclass(&p.To) + 1
|
|
p.To.Class = int8(cls)
|
|
}
|
|
cls--
|
|
switch cls {
|
|
default:
|
|
fmt.Printf("unknown class %d %v\n", cls, p)
|
|
|
|
case C_ZCON,
|
|
C_SCON,
|
|
C_ADD0CON,
|
|
C_AND0CON,
|
|
C_ADDCON,
|
|
C_ANDCON,
|
|
C_UCON,
|
|
C_LCON,
|
|
C_NONE,
|
|
C_SBRA,
|
|
C_LBRA,
|
|
C_ADDR,
|
|
C_TEXTSIZE:
|
|
break
|
|
|
|
case C_HI,
|
|
C_LO:
|
|
s.set.cc |= E_HILO
|
|
|
|
case C_FCREG:
|
|
s.set.cc |= E_FCR
|
|
|
|
case C_MREG:
|
|
s.set.cc |= E_MCR
|
|
|
|
case C_ZOREG,
|
|
C_SOREG,
|
|
C_LOREG:
|
|
cls = int(p.To.Reg)
|
|
s.used.ireg |= 1 << uint(cls-REG_R0)
|
|
if ad != 0 {
|
|
break
|
|
}
|
|
s.size = uint8(sz)
|
|
s.soffset = c.regoff(&p.To)
|
|
|
|
m := uint32(ANYMEM)
|
|
if cls == REGSB {
|
|
m = E_MEMSB
|
|
}
|
|
if cls == REGSP {
|
|
m = E_MEMSP
|
|
}
|
|
|
|
if ar != 0 {
|
|
s.used.cc |= m
|
|
} else {
|
|
s.set.cc |= m
|
|
}
|
|
|
|
case C_SACON,
|
|
C_LACON:
|
|
s.used.ireg |= 1 << (REGSP - REG_R0)
|
|
|
|
case C_SECON,
|
|
C_LECON:
|
|
s.used.ireg |= 1 << (REGSB - REG_R0)
|
|
|
|
case C_REG:
|
|
if ar != 0 {
|
|
s.used.ireg |= 1 << uint(p.To.Reg-REG_R0)
|
|
} else {
|
|
s.set.ireg |= 1 << uint(p.To.Reg-REG_R0)
|
|
}
|
|
|
|
case C_FREG:
|
|
if ar != 0 {
|
|
s.used.freg |= 1 << uint(p.To.Reg-REG_F0)
|
|
} else {
|
|
s.set.freg |= 1 << uint(p.To.Reg-REG_F0)
|
|
}
|
|
if ld != 0 && p.From.Type == obj.TYPE_REG {
|
|
p.Mark |= LOAD
|
|
}
|
|
|
|
case C_SAUTO,
|
|
C_LAUTO:
|
|
s.used.ireg |= 1 << (REGSP - REG_R0)
|
|
if ad != 0 {
|
|
break
|
|
}
|
|
s.size = uint8(sz)
|
|
s.soffset = c.regoff(&p.To)
|
|
|
|
if ar != 0 {
|
|
s.used.cc |= E_MEMSP
|
|
} else {
|
|
s.set.cc |= E_MEMSP
|
|
}
|
|
|
|
case C_SEXT,
|
|
C_LEXT:
|
|
s.used.ireg |= 1 << (REGSB - REG_R0)
|
|
if ad != 0 {
|
|
break
|
|
}
|
|
s.size = uint8(sz)
|
|
s.soffset = c.regoff(&p.To)
|
|
|
|
if ar != 0 {
|
|
s.used.cc |= E_MEMSB
|
|
} else {
|
|
s.set.cc |= E_MEMSB
|
|
}
|
|
}
|
|
|
|
/*
|
|
* flags based on 'from' field
|
|
*/
|
|
cls = int(p.From.Class)
|
|
if cls == 0 {
|
|
cls = c.aclass(&p.From) + 1
|
|
p.From.Class = int8(cls)
|
|
}
|
|
cls--
|
|
switch cls {
|
|
default:
|
|
fmt.Printf("unknown class %d %v\n", cls, p)
|
|
|
|
case C_ZCON,
|
|
C_SCON,
|
|
C_ADD0CON,
|
|
C_AND0CON,
|
|
C_ADDCON,
|
|
C_ANDCON,
|
|
C_UCON,
|
|
C_LCON,
|
|
C_NONE,
|
|
C_SBRA,
|
|
C_LBRA,
|
|
C_ADDR,
|
|
C_TEXTSIZE:
|
|
break
|
|
|
|
case C_HI,
|
|
C_LO:
|
|
s.used.cc |= E_HILO
|
|
|
|
case C_FCREG:
|
|
s.used.cc |= E_FCR
|
|
|
|
case C_MREG:
|
|
s.used.cc |= E_MCR
|
|
|
|
case C_ZOREG,
|
|
C_SOREG,
|
|
C_LOREG:
|
|
cls = int(p.From.Reg)
|
|
s.used.ireg |= 1 << uint(cls-REG_R0)
|
|
if ld != 0 {
|
|
p.Mark |= LOAD
|
|
}
|
|
s.size = uint8(sz)
|
|
s.soffset = c.regoff(&p.From)
|
|
|
|
m := uint32(ANYMEM)
|
|
if cls == REGSB {
|
|
m = E_MEMSB
|
|
}
|
|
if cls == REGSP {
|
|
m = E_MEMSP
|
|
}
|
|
|
|
s.used.cc |= m
|
|
|
|
case C_SACON,
|
|
C_LACON:
|
|
cls = int(p.From.Reg)
|
|
if cls == 0 {
|
|
cls = REGSP
|
|
}
|
|
s.used.ireg |= 1 << uint(cls-REG_R0)
|
|
|
|
case C_SECON,
|
|
C_LECON:
|
|
s.used.ireg |= 1 << (REGSB - REG_R0)
|
|
|
|
case C_REG:
|
|
s.used.ireg |= 1 << uint(p.From.Reg-REG_R0)
|
|
|
|
case C_FREG:
|
|
s.used.freg |= 1 << uint(p.From.Reg-REG_F0)
|
|
if ld != 0 && p.To.Type == obj.TYPE_REG {
|
|
p.Mark |= LOAD
|
|
}
|
|
|
|
case C_SAUTO,
|
|
C_LAUTO:
|
|
s.used.ireg |= 1 << (REGSP - REG_R0)
|
|
if ld != 0 {
|
|
p.Mark |= LOAD
|
|
}
|
|
if ad != 0 {
|
|
break
|
|
}
|
|
s.size = uint8(sz)
|
|
s.soffset = c.regoff(&p.From)
|
|
|
|
s.used.cc |= E_MEMSP
|
|
|
|
case C_SEXT:
|
|
case C_LEXT:
|
|
s.used.ireg |= 1 << (REGSB - REG_R0)
|
|
if ld != 0 {
|
|
p.Mark |= LOAD
|
|
}
|
|
if ad != 0 {
|
|
break
|
|
}
|
|
s.size = uint8(sz)
|
|
s.soffset = c.regoff(&p.From)
|
|
|
|
s.used.cc |= E_MEMSB
|
|
}
|
|
|
|
cls = int(p.Reg)
|
|
if cls != 0 {
|
|
if REG_F0 <= cls && cls <= REG_F31 {
|
|
s.used.freg |= 1 << uint(cls-REG_F0)
|
|
} else {
|
|
s.used.ireg |= 1 << uint(cls-REG_R0)
|
|
}
|
|
}
|
|
s.set.ireg &^= (1 << (REGZERO - REG_R0)) /* R0 can't be set */
|
|
}
|
|
|
|
/*
|
|
* test to see if two instructions can be
|
|
* interchanged without changing semantics
|
|
*/
|
|
func (c *ctxt0) depend(sa, sb *Sch) bool {
|
|
if sa.set.ireg&(sb.set.ireg|sb.used.ireg) != 0 {
|
|
return true
|
|
}
|
|
if sb.set.ireg&sa.used.ireg != 0 {
|
|
return true
|
|
}
|
|
|
|
if sa.set.freg&(sb.set.freg|sb.used.freg) != 0 {
|
|
return true
|
|
}
|
|
if sb.set.freg&sa.used.freg != 0 {
|
|
return true
|
|
}
|
|
|
|
/*
|
|
* special case.
|
|
* loads from same address cannot pass.
|
|
* this is for hardware fifo's and the like
|
|
*/
|
|
if sa.used.cc&sb.used.cc&E_MEM != 0 {
|
|
if sa.p.Reg == sb.p.Reg {
|
|
if c.regoff(&sa.p.From) == c.regoff(&sb.p.From) {
|
|
return true
|
|
}
|
|
}
|
|
}
|
|
|
|
x := (sa.set.cc & (sb.set.cc | sb.used.cc)) | (sb.set.cc & sa.used.cc)
|
|
if x != 0 {
|
|
/*
|
|
* allow SB and SP to pass each other.
|
|
* allow SB to pass SB iff doffsets are ok
|
|
* anything else conflicts
|
|
*/
|
|
if x != E_MEMSP && x != E_MEMSB {
|
|
return true
|
|
}
|
|
x = sa.set.cc | sb.set.cc | sa.used.cc | sb.used.cc
|
|
if x&E_MEM != 0 {
|
|
return true
|
|
}
|
|
if offoverlap(sa, sb) {
|
|
return true
|
|
}
|
|
}
|
|
|
|
return false
|
|
}
|
|
|
|
func offoverlap(sa, sb *Sch) bool {
|
|
if sa.soffset < sb.soffset {
|
|
if sa.soffset+int32(sa.size) > sb.soffset {
|
|
return true
|
|
}
|
|
return false
|
|
}
|
|
if sb.soffset+int32(sb.size) > sa.soffset {
|
|
return true
|
|
}
|
|
return false
|
|
}
|
|
|
|
/*
|
|
* test 2 adjacent instructions
|
|
* and find out if inserted instructions
|
|
* are desired to prevent stalls.
|
|
*/
|
|
func conflict(sa, sb *Sch) bool {
|
|
if sa.set.ireg&sb.used.ireg != 0 {
|
|
return true
|
|
}
|
|
if sa.set.freg&sb.used.freg != 0 {
|
|
return true
|
|
}
|
|
if sa.set.cc&sb.used.cc != 0 {
|
|
return true
|
|
}
|
|
return false
|
|
}
|
|
|
|
func (c *ctxt0) compound(p *obj.Prog) bool {
|
|
o := c.oplook(p)
|
|
if o.size != 4 {
|
|
return true
|
|
}
|
|
if p.To.Type == obj.TYPE_REG && p.To.Reg == REGSB {
|
|
return true
|
|
}
|
|
return false
|
|
}
|
|
|
|
var Linkmips64 = obj.LinkArch{
|
|
Arch: sys.ArchMIPS64,
|
|
Init: buildop,
|
|
Preprocess: preprocess,
|
|
Assemble: span0,
|
|
Progedit: progedit,
|
|
DWARFRegisters: MIPSDWARFRegisters,
|
|
}
|
|
|
|
var Linkmips64le = obj.LinkArch{
|
|
Arch: sys.ArchMIPS64LE,
|
|
Init: buildop,
|
|
Preprocess: preprocess,
|
|
Assemble: span0,
|
|
Progedit: progedit,
|
|
DWARFRegisters: MIPSDWARFRegisters,
|
|
}
|
|
|
|
var Linkmips = obj.LinkArch{
|
|
Arch: sys.ArchMIPS,
|
|
Init: buildop,
|
|
Preprocess: preprocess,
|
|
Assemble: span0,
|
|
Progedit: progedit,
|
|
DWARFRegisters: MIPSDWARFRegisters,
|
|
}
|
|
|
|
var Linkmipsle = obj.LinkArch{
|
|
Arch: sys.ArchMIPSLE,
|
|
Init: buildop,
|
|
Preprocess: preprocess,
|
|
Assemble: span0,
|
|
Progedit: progedit,
|
|
DWARFRegisters: MIPSDWARFRegisters,
|
|
}
|